Has anyone ported the PCIe reference design for App Note 532 to the Arria II GX dev kit - and had the PC host GUI work? If so, can you share the project or any insight? -Thanks

I am also trying to port AN532 to the Arria II GX Dev Board but having no luck. What I did find in the PCI Express Compiler User Guide in the SOPC Builder Design Flow Chapter 2 is a paragraph saying " For Stratix IV GX and Arria II GX designs, you must instantiate the ALT_RECONFIG megafunction and connect it to three pins from your SOPC Builder system that are required to dynamically reconfigure the transceiver..... reconfig_Clk_<PCIe_Compiler_Instance_name> reconfig_fromgxb_<PCIe_Compiler_Instance_name> reconfig_togxb_<PCIe_Compiler_Instance_name>" But I still couldn't get the LINUX system to recognise the board. Whereas loading the factory default works OK with LINUX showing the correct Device ID etc. Is your FPGA design working but you are only having problems with the GUI OR you are having problems with both?

Hi all, i'm trying to port AN532 to the Arria II GX devkit, too. I encounterd the very same problems that are mentioned above. I did not yet try to connect the reconfig block. Can you tell me if it helps? I sucsessfully created a project from the megawizard example chaining dma and got it working with Quartus 9.1 . Even the linuxdriver altpciechdma works once after a reboot. I think this is a x8-pcie-endpoint. I need a x1-pcie-endpoint, so i connected the signals PCIE_RX_{P,N}0 and PCIE_TX_{P,N}0 to the pins mentioned in the "Arria II GX FPGA Development Board" on the sopcsystem that is like that one in AN532. It did not work with my own sopcsystem and i thought that could be the problem. Has someone created a working sopcsystem for the Arria II GX Development Board? Regards, Frederik

Hi Frederik, I did managed to get AN532 ported to the Arria II GX dev board but endure a lot of pain on the way. You MUST connect the reconfig block in, also don't follow Altera example of using the ref_clk divided by 2 as the reconfig_clk. The ref_clk should only go to the PCIe IP itself and nothing else. The reconfig_clk range of 37.5MHz to 50MHz must be adhere to. My design path is via the SOPC Builder and not with the megawizard method. This might help you but it is only x4 lane : set_location_assignment PIN_AE29 -to pcie_refclk set_location_assignment PIN_N1 -to pcie_reset_n set_location_assignment PIN_AN33 -to rx0 set_location_assignment PIN_AL33 -to rx1 set_location_assignment PIN_AJ33 -to rx2 set_location_assignment PIN_AG33 -to rx3 set_location_assignment PIN_AM31 -to tx0 set_location_assignment PIN_AK31 -to tx1 set_location_assignment PIN_AH31 -to tx2 set_location_assignment PIN_AF31 -to tx3 set_location_assignment PIN_AJ19 -to clk_in set_location_assignment PIN_N10 -to reset_n Regards, Peter

Hi PeterCH, thanks for the rapid answer. I don't see a reset_n in my design. And I have some pins you didn't mention: gxb_powerdown_pcie_compiler_0 and pll_powerdown_pcie_compiler_0 (inputs) and rate_ext_pcie_compiler_0 and clock outputs (output). I'm using Quartus 10.0 . Don't you see this signals? Should I try Quartus 9.1 rather than the new version? My clock was connected to F18(p) and F17(n). I will test your locations. Regards, Frederik

Frederik, All inputs at the top level can be left unconnected. In VHDL, just declare a signal called gxb_powerdown_pcie_compiler_0_sig and connect that to the vhdl instantiation. DO the same for the other inputs. You can use the 125Mhz clock output from the PCIe IP as your application input clock instead of the local_clock. The MOST IMPORTANT signals is actually the test_in, see below: test_in(39 downto 16) <= (others => '0'); -- selects the layer to output onto the test_out bus test_in(15 downto 13) <= "000"; -- selects the Lane test_in(12) <= '0'; -- selects VC test_in(11 downto 8) <= "0010"; -- 0000 = Transaction Layer, 0010 = PHY-MAC outputs test_in(7) <= '0'; -- Disable low power state negotiation test_in(6 downto 5) <= "00"; -- b5 = completely disables compliance mode; never enter compliance mode -- b6 = forces compliance mode. test_in(4) <= '0'; -- Remote Boot mode test_in(3) <= '1'; -- FPGA mode. Set to '1' for an FPGA implementation in order to appear compliant to other PCI Express components. test_in(2) <= '0'; -- Descramble mode test_in(1) <= '0'; -- Loopback Master test_in(0) <= '0'; -- Simulation mode Regards, Peter

Anyone ported AN532 PCIe to Arria2GX dev kit?

14 Replies

Altera_Forum
Honored Contributor
15 years ago
Hi Peter,

I just found AN 558: Implementing Dynamic Reconfiguration in Arria II GX Devices. That helps. I found the reconfig block in the Megawizard. I will test it now.

Regards,

Frederik
Altera_Forum
Honored Contributor
15 years ago
Ok, I do see the device under linux with lspci.

Thanks a lot!
Altera_Forum
Honored Contributor
14 years ago
Hey Frederik

Having same problem with porting AN532 to Arria II GX. It would be great if you could share the wrapper module and some tips.
Altera_Forum
Honored Contributor
14 years ago
Hope it might help some one like me.

Here I am attaching working PCI - SOPC reference design for Arria II GX Dev kit.
pci.zip1 MB

Forum Discussion

Anyone ported AN532 PCIe to Arria2GX dev kit?

14 Replies

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