Forum Discussion
Altera_Forum
Honored Contributor
15 years agoHi Frederik,
I did managed to get AN532 ported to the Arria II GX dev board but endure a lot of pain on the way. You MUST connect the reconfig block in, also don't follow Altera example of using the ref_clk divided by 2 as the reconfig_clk. The ref_clk should only go to the PCIe IP itself and nothing else. The reconfig_clk range of 37.5MHz to 50MHz must be adhere to. My design path is via the SOPC Builder and not with the megawizard method. This might help you but it is only x4 lane : set_location_assignment PIN_AE29 -to pcie_refclk set_location_assignment PIN_N1 -to pcie_reset_n set_location_assignment PIN_AN33 -to rx0 set_location_assignment PIN_AL33 -to rx1 set_location_assignment PIN_AJ33 -to rx2 set_location_assignment PIN_AG33 -to rx3 set_location_assignment PIN_AM31 -to tx0 set_location_assignment PIN_AK31 -to tx1 set_location_assignment PIN_AH31 -to tx2 set_location_assignment PIN_AF31 -to tx3 set_location_assignment PIN_AJ19 -to clk_in set_location_assignment PIN_N10 -to reset_n Regards, Peter