Any ideas why this code isn't working

After detecting the falling edge of the start bit, the first delay has to be a half bit time, because the data has to be sampled at the nominal center.

There are dozens (or hundreds?) of Verilog and VHDL UART examples in text books and on the internet. Some have been posted at Altera Forum. You can try to adapt an existing one, but it's of course instructive to design your own.

Two remarks on your coding style:

You can save of lot of text by using more intelligent Verilog constructs:

bitstreamin <= {bitstreamin, GPSIN}; // assuming a decreasing bit index

or use a loop for the assignment of multiple bits