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Altera_Forum's avatar
Altera_Forum
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16 years ago

AND vs XOR gate

Im sorry if my post doesnt belong to here. Just a short question: Which one is larger in term of implementation? AND gate or XOR gate ? thanks
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

FPGAs use lookup tables. The lookup tables are programmed with the output of the logic you are implementing. For a two input AND or XOR gate this is what you can expect the LUT to look like:

address AND XOR

0 0 0

1 0 1

2 0 1

3 1 0

The address is just your two inputs grouped together. In other words if you have y = A & B, then the address is just the bits A B grouped together. These form the address input of the lookup table and the data that comes out of the lookup table is signal 'y'.

Because an AND or XOR gate both fit into a single lookup table there shouldn't be any difference in the operation speed since this is determined by how fast the data in the LUT can be accessed (amongst other things like pipelining, routing delays, etc...)