An interesting phenomenon when using LVDS ip core in EP4CE55F23C8

Hi,

i came cross an interesting phenomenon when using LVDS ip core in my project.

the FPGA is EP4CE55F23C8. it receives five pairs of lvds inputs from outside with clock of 420MHz, the input lvds data is 7-bit as an unit, that is, the deserilized data is 7-bit per ground, 35-bit for 5 pairs lvds inputs at the clock of 60MHz, this 35-bit then is truncated to 24-bit(M1,M2,M3) and written to a 24-bit fifo.

The interesting thing is: when i change the written byte-order, the result is different.

For example, assume M1 is the MSB-8bit of the 24-bit data written into fifo, that is, the normal byte order should be {M1a,M2a,M3a}, however, when i reorganized the byte order to be {M3b,M2b,M1b} and wrote into the fifo, the M1a is not equal to M1b, and i did not change anything except the byte-order written into fifo!

In fact, my own logic is very simple, it reads serial data from LVDS IP Core provided by Altera, does serial-to-parallel conversion and writes the parallel data into a fifo, then uploads the fifo data to PC to analyze.

More interesting, when i change something irrelavent, e.g. a counter number used to stop receiving data from LVDS Core in my own logic, the uploaded data is different when the input data is same!

Any idea?

Thanks a lot.