Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorAn fpga prototyping dilemma.
I was trying to create an IP core for lightweight block cipher MANTIS. The simulation of the Verilog code given below was successfully completed. But,when I try to form IPcore using DE0 cyclone 3.T...
Altera_ForumHonored Contributor
Honored ContributorLike I said before, for loops unroll during synthesis to create ALL of the hardware needed to create the logic, they do not work in a temporal fashion like in software. For loops are generally used to replicate hardware.
I highly suggest starting this again. Try to think about your circuit BEFORE you write any code. All of your assignments are blocking assignments - try and code the entire design with non-blocking assignments. As good practice, blocking assignments should only be used for wires/conitnuous assignments, with non-blocking for everything else. Your current design will have a very very slow fmax due to the huge amount of combinatorial logic it will employ.
