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Altera_Forum
Honored Contributor
Honored ContributorAn fpga prototyping dilemma.
I was trying to create an IP core for lightweight block cipher MANTIS. The simulation of the Verilog code given below was successfully completed. But,when I try to form IPcore using DE0 cyclone 3.T...
Altera_ForumHonored Contributor
Honored ContributorNo,I don't have a circuit diagram.I coded this on the basis of a block diagram.
Is using a for loop for repeating round functions bad? I know for loop doesn't work like software and circuit replicates.
