Forum Discussion
Altera_Forum
Honored Contributor
8 years agoAn fpga prototyping dilemma.
I was trying to create an IP core for lightweight block cipher MANTIS. The simulation of the Verilog code given below was successfully completed. But,when I try to form IPcore using DE0 cyclone 3.T...
Altera_Forum
Honored Contributor
8 years agoBut you didn't answer the questions.
Have you got a circuit diagram you used before you wrote the code? How long did you run the simulation for? You may not have run it very long, the simulation will likely slow the repeat. And the use of for loops implies you think this is software. Or is not. Software coding style will result in firmware that doesn't work well if it works at all. You really should study a good text book or tutorial on digital logic design.