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Altera_Forum's avatar
Altera_Forum
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8 years ago

An fpga prototyping dilemma.

I was trying to create an IP core for lightweight block cipher MANTIS. The simulation of the Verilog code given below was successfully completed. But,when I try to form IPcore using DE0 cyclone 3.T...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

I kept it running.

I needed round functions and inverse round functions to be repeated and them to use a round constant based on no of current round.That's why I used for loop.

S0 doesn't have cipher ,ci and only s9 has it so would it matter.

This simulation is working perfectly fine for me in modelsim.

Only thing changed is replacing all inputs and output excluding clk to wire and not using a test bench.