Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorAn fpga prototyping dilemma.
I was trying to create an IP core for lightweight block cipher MANTIS. The simulation of the Verilog code given below was successfully completed. But,when I try to form IPcore using DE0 cyclone 3.T...
Altera_ForumHonored Contributor
Honored ContributorS9 sets next state to s0. How long did you run the simulation for?
Also, your verilog looks like you're writing some software. For loops get expanded during synthesis into parrellel or sequential circuits. Did you draw a diagram of your intended circuit design before you write any code?
