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Altera_Forum
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12 years ago

An all-in-one Software Defined Radio platform

Hi, I'm building the analog front end for my software defined radio receiver architecture. The ADC will directly sample the bandwidth of interest to basband where the the information can be pas...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Your FPGA selection needs to be based on your ADC selection. For example

1. Logic Interface; 3.3V LVCMOS, LVDS, or transceivers (JESD204)?

2. Interface clock frequency; what is the bus speed into the FPGA?

Cheers,

Dave