altsyncram in simple dual-port mode

Hi Shayle,

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I have determined that the altsyncram function is working correctly and that problems I had with it were really more of trying to deal with my perceived belief that Modelsim/Quartus netlist extraction wasn't working correctly.

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I'm glad you have it working.

I would discourage using whatever technique that resulted in a testbench that uses Tcl to force signals onto the design. If you are serious about HDL coding, then you need to learn how to code for both synthesis and simulation using VHDL and/or Verilog/SystemVerilog.

I know, its a lot to come to grips with when you are starting out. But when you have some time, make the effort to learn how to use Modelsim. It will pay off pretty quickly when designs 'just work' in hardware, given that you have them working in the simulator. Its a lot easier to see all the signals in Modelsim than it is to tap them with SignalTap, but then it is nice to see the SignalTap waveforms matching simulation too.

Cheers,

Dave

Hi Dave,

Yes, good advice. All very true.

I will do that later, when I get back to Verilog. For now, I am using AHDL and letting Quartus generate the netlist.

When I get a chance, I will follow your recommendation.

Thanks,

Shayle