altsyncram in simple dual-port mode

Hi Kaz and Dave,

As you described, I have determined that the altsyncram function is working correctly and that problems I had with it were really more of trying to deal with my perceived belief that Modelsim/Quartus netlist extraction wasn't working correctly.

I have now determined that Modelsim is also working correctly and that the issue is that Modelsim required >0 ns of hold time on the write date port input. This result is in line with what I believe you were getting at earlier in the thread along with a hint I noticed in that the data output Modelsin was showing was delayed by 1 ns from the clock (tCO time).

As the netlist is generated by Quartus without timing info, i.e. only by Analysis and Synthesis, I was expecting only a functional simulation. However, I see Modelsim still includes timing, at least in some ways, and so for at least some input I must have greater that 0 ns of hold time.

That is the interesting solution to this problem, as simple as it now seems.

I agree that I should look into more sophistigated types of testbench simulation, which can also provide the advantage of interactive simulation. But for now, for this work, the *.do file feeding into Modelsim is good and works well, and uses the Altera model of the IP, though this exercise has certainly underlined the importance of understanding even the most subtle aspects of the tools used (such as the >0 ns hold time on the inputs in the stimulus file).

Thank you again for your help in getting me to this understanding and achieving success in my design work.

Shayle

:)