altsyncram in simple dual-port mode

Hi Shayle,

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Attached is the Modelsim folder that includes my .do file and the .vho netlist file that Quartus created from the original AHDL design.

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This is not a testbench though. All you have uploaded is the .vho file.

A testbench should create an instance of the component and then drive signals onto the component ports, and check the response on the output ports. You really need to learn how to do this.

There's an example in this thread:

http://www.alteraforum.com/forum/showthread.php?t=32386

Cheers,

Dave