altsyncram in simple dual-port mode

Now you confirmed what I said:

input data and address are registered, so data written will be coincidental with address but data read out will not be be coincidental and must be delayed by one clock (what you call mismatch)

so your first posted signaltap waves are correct.

Now the issue is why modelsim is different. I believe it is not different in this respect. It shows one clock delay as well.

You are not comparing like by like as you are not dealing with a synthesisable testbench. It looks like your clocking changes in between. Show us the clock waveforms in both cases and you will see.