altsyncram in simple dual-port mode

Hi Dave and Kaz (and others),

Attached is the Modelsim folder that includes my .do file and the .vho netlist file that Quartus created from the original AHDL design.

I believe the Modelsim waveform shows the inputs matching the values and timing of the Signal Tap waveforms, which is why I suspect a problem in Modelsim or in Quartus's netlist generation...perhaps the latter makes more sense. But maybe I have missed something.

As for the Signal Tap display, the megafunction wizzard diagram shows one register on each of the data, address, and wren control signals. Normally that means that the data presented at the same clock edge as the wren will go into the address that is presented at that same clock edge. I have suspected, as Kaz also hypothesized, that there is a mismatch in altsyncram internal pipelining between the address path with respect to data and wren. Although that could be handled by an additional, external register delay on the write address port input, there seems to be other problems as well.

I have attached a document showing two Signal Tap drawings. The first simply adds the extra, external write address delay to the write address port and has a continuous, incrementing write address, regardless of the other inputs. This works as expected.

The second drawing shows the same design and inputs, but with the address being set to exactly what is needed, matching the data and wren. Here, three writes fail to occur that should have occurred, and the only difference is that the write address is not continuously incrementing.

Any insights you have to this problem would be greatly appreciated!

Thank you,

Shayle