altsyncram in simple dual-port mode

Thank you Kaz. I believe all clocking is rising edge.

I have attached an update of data captured showing what I believe to be incorrect behavior in both the FPGA instantiation and in Modelsim, and also showing the two not matching each other for identical designs.

The drawing also has the text explanation included below. Please let me know if you have further questions on my description. Your help is greatly appreciated!

Thank you,

Shayle

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From attached drawing:

Top picture:

Signal Tap capture of altsyncram behavior in Stratix III, showing read data correct in sequence but at wrong addresses. Output mode is non-registered, so data 1 should be at address 0, data 9 at address 1, etc.

Bottom Picture:

Modelsim behavior of identical altsyncram design showing correct data from address 3 and above. However, data at addresses 0, 1, and 2 are incorrect.

I suspect there is some internal pipelining going on in the altsyncram function that I don't know about, and that Modelsim models that differently than that of the actual instantiation.

Any help or insights are greatly appreciated.