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raviganesh's avatar
raviganesh
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5 years ago

ALTPLL Clock switchover in Cyclone 10 LP

I am using the ALTPLL to generate a 80MHz clock from a 48MHz clock. This is fine. Later when an independent clean 80MHz clock is available I am switching over to this clock by using the clock switch...
raviganesh's avatar
raviganesh
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Hi Chin,

Thanks for the clarifications. As a feedback if this point is captured in the documentation as well as the ALTPLL IP Catalog software it would be great.

As a simple workaround to the dynamic configuration I am spoofing the 48MHz clock as 80MHz in the IP Catalog. i.e I mention inClk0 as 80MHz but give a 48MHz. This is a temporary arrangement until I get the clean 80MHz inclk1 in my application. It is working fine. But are there any design pitfalls in the PLL that would give random problems in field?