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Altera_Forum
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15 years ago

ALTMEMPHY Debug GUI: Fails Read Resynch Phase Cal Rst

I'm debugging a DDR2 SO-DIMM design that doesn't work (the example top design seemingly doesn't do anything). I enabled the debug interface per the EMI handbook (debug section) and ran the Debug GUI. The stage 'Read resynchronisation phase calibration - reset' fails with result code 0xa2177307.

Any idea where to start looking for errors? Would it make sense to lower the speed of the DDR2 interface (currently 200 MHz on an Arria II GX)? Any other tips?

The only possible relevant warning is the following from analysis & synthesis:

Warning: PLL "HPC1_example_top:inst1|HPC1:HPC1_inst|HPC1_controller_phy:HPC1_controller_phy_inst|HPC1_phy:HPC1_phy_inst|HPC1_phy_alt_mem_phy:HPC1_phy_alt_mem_phy_inst|HPC1_phy_alt_mem_phy_clk_reset:clk|HPC1_phy_alt_mem_phy_pll:half_rate.pll|altpll:altpll_component|altpll_u9p3:auto_generated|pll1" has parameters clk2_multiply_by and clk2_divide_by specified but port CLK[2] is not connected

Is this normal?

The .doom file is attached.

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    I have today worked some more on this problem. It turns out that the exact same error occurs when the SO-DIMM module is removed from the socket. Interestingly enough, all the previous initialization reports as okay by the Debug GUI - seems odd.

    I have also obtained more signaltap II signals at the point of failure. The attached JPG shows all signals recommended to be added to the signaltap trace (EMI Vol 4, section III - 'Debugging Hardware'). Not much can be gleaned from this information except that the s_rrp_reset state exited after 2 ticks and the FSM ended up in the s_non_operational (expected since the calibration failed).

    I will reverse engineer the details from the VHDL sources...