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Honored ContributorALTMEMPHY - No Clocks - RefClk Slew Rate Requirements?
I'm debugging a Cyclone IV E design. The DDR2 interface is dead in hardware but simulates okay. Signaltap shows two out of three DIMM clocks dead. I scoped the 50 MHz reference clock and the rise and...
Altera_ForumHonored Contributor
Honored ContributorPlease disregard; I found the error. The HPCII controller was configured for two chip select signals while the DIMM only uses one! The calibration and sample test now work fine.
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