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Altera_Forum
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10 years ago

ALTMEMPHY - No Clocks - RefClk Slew Rate Requirements?

I'm debugging a Cyclone IV E design. The DDR2 interface is dead in hardware but simulates okay. Signaltap shows two out of three DIMM clocks dead. I scoped the 50 MHz reference clock and the rise and...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

I have, via Signaltap, traced the error to a failure in the below altmemphy state:

State.s_rrp_seek Read resynchronization phase setup stage: set PLL to center of valid window.

dgrb_ctrl.command_err Error in the data gather read bias block.

dgrb_ctrl.command_result[7..0] Data gather read block (DGRB) error code.

The error code is 05h.

Can anyone shed some light on what, exactly, this means?

I will do my best to Google for an answer...

STP screenshot attached.

Thanks!