ALTMEMPHY - No Clocks - RefClk Slew Rate Requirements?

Thanks Alex for the response. It looks like the ALTMEMPHY/HPCII Controller PLLs lock since I'm actually seeing the correct clock frequency being output onto the DIMM connector.

Edit: I have confirmed via signaltap that the PLL locks onto the reference clock right before the test_status transitions from 00h to 01h.

There are however a few strange behaviors I have not seen in my prior ALTMEMPHY DDR2 interface design:

1) I cannot see more than one of the three DDR2 clocks in signaltap (six when counting the negative signals, too). Upon inspection of the schematics, the clock signal that is seen (clk0+) is connected to a pin part of a DQ group, while the other five (clk0-, clk1+, clk1-, clk2+, clk2-) are connected to regular I/O pins. Surely, it is not a coincidence that the only clock seen in STP is the one connected to a DQ-capable pin? Also, note that all six of these clock signals output correct SSTL-18 frequencies (I've tested 125 MHz as well as 133 MHz).

2) The ALTMEMPHY Debug Toolkit cannot connect to the ALTMEMPHY instance. I have enabled the 'debug port' per the ALTMEMPHY IP User Guide (adding alt_jtagavalon instance to the Megawizard top-level design). When spawning the ALTMEMPHY debug toolkit it doesn't show any instance to connect to. I've in the past done this successfully for an ALTMEMPHY-based DDR2 HPCII controller for Arria II so should work for Cyclone IV too?

3) No activity can be seen in the signaltap trace except for the test_status changing from 0 to 1 half-way in the trace.

4) Everything else works properly on this board (lots of I/Os, Ethernet interface etc) so it is clear that the FPGA is functioning. I'm strongly suspecting the incorrectly placed clock pins to be the culprit but can't prove this. It would be unfortunate to re-spin this expensive board without knowing the exact cause (and cure) of the issue.

Finally; I have a good scope. A 2.5 GHz active probe was used and the scope is a 13 GHz Agilent Infiniuum. Also, the 50 MHz reference clock tree can't be cut on the board since routed on inner layers.