Honored Contributor
Honored ContributorYes - a number of the factors you mention may adversely affect the ability of the PLL to lock. A poor slew rate will affect the perceived high/low time ratio the PLL sees, which it will care about. Point of note: is your oscilloscope up to measuring this accurately? Using a scope with an unsuitably low bandwidth will also have this effect, even if the wave shape is in fact good.
Having six loads on the oscillator is also going to affect the wave shape and could easily cause the PLL further locking problems. Does the PLL report it has lock? You can implement the PLL with such an output signal, typically available by default. Try unloading the oscillator. Can you remove some of the loads? This will need to be done carefully so as not to leave stubs. You may end up having to cut tracks to do this effectively. As for the poor clock pair selection - only a re-spin is going to solve that. However, a bit of a long shot but - depending on the signalling standard of your clock source, you may find that one half of your differential clock could be used as a single ended input clock to the FPGA. Cheers, Alex
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