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Altera_Forum
Honored Contributor
Honored ContributorALTLVDS_RX Old & New
Can anyone tell my why ALTLVDS_RX with an external PLL requires; 1 clock at data_rate/2 when using Quartus 13.1 1 clock at data_rate + 1 clock at data_rate/deser-factor when using Quartus ...
Altera_ForumHonored Contributor
Honored ContributorAre you sure the first picture is targeting Cyclone V? When I launch Q13.1 and create altlvds_rx /8 with external PLL, I get the exact same text as your second one. If I change it to Cyclone IV(or any device that doesn't have True LVDS), then I get the text in your first picture.
Also note that your first screenshot only has one clock coming in, where True LVDS needs two. And the clock rate it talks about is /2 the data rate, which is exactly what the clock should be if you don't use True LVDS and instead build it out of a DDR input register. So I'm pretty certain the second screen shot is doing True LVDS while the first one is not, and instead building it out of DDR input registers. I'm not quite sure why though, but it shouldn't be a 13.1/16.1 issue. If you have further problems, please include the 13.1 output .v/.vhd file and I can open it in Q13.1. (Perhaps the option to match project is checked and the project is CIV, while the greyed out option above it says CV?)
