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Honored Contributor
Honored ContributorALTLVDS_RX Old & New
Can anyone tell my why ALTLVDS_RX with an external PLL requires; 1 clock at data_rate/2 when using Quartus 13.1 1 clock at data_rate + 1 clock at data_rate/deser-factor when using Quartus ...
Altera_ForumHonored Contributor
Honored ContributorTrue LVDS uses dedicate silicon in Cyclone V, so it shouldn't be redesigned. In both cases the PLL should have three outputs:
c0: This is the high-speed clock that runs at the serial rate and clocks in the data. (True LVDS does not use the DDR registers. Instead, it captures with a single register running at the full rate, thereby avoiding any issues due to rise/fall variation on the clock tree) c1: This is an enable bit for loading this serial data into a parallel register. That is why it's duty cycle is 1/8th the clock period c2: This is your core clock, with a 50% duty cycle, that runs at the parallel data rate. Please look at the following: https://www.altera.com/support/support-resources/knowledge-base/solutions/rd06142011_962.html Hopefully that helps.
