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Altera_Forum
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9 years ago

ALTLVDS_RX->LVDS serdes Link Training

Implementing Receiver interface. From transmitter we have 8 LVDS data channel and 1 LVDS sync channel. From sync channel we use to get training pattern which will be available in data channel for lin...
Altera_Forum's avatar
Altera_Forum
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9 years ago

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Hi Rysc,

Yes, DCO is the source sycnrous clock, together with the output LVDS data. The FCO is the fram clock output, which will indicate the data word edge. Normally, FCO would be process like LVDS output data channel. That's why i said it will consume fpga lvds_rx channels.

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If the ADC used has a loadable testpattern you could do without the FCO signals and do a bitslip alignment on each ADC channel.