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Altera_Forum
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9 years ago

ALTLVDS_RX->LVDS serdes Link Training

Implementing Receiver interface. From transmitter we have 8 LVDS data channel and 1 LVDS sync channel. From sync channel we use to get training pattern which will be available in data channel for lin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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That is another big benefit of DPA. Since each channel aligns itself, you can use a single PLL for all three interfaces.

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Hi Rysc,

Thanks for you reply.

Do I need to match the trace lines' length equeal among the 3 ADC output LVDS signals outside the fpga? Or just make the ADCs sampling clock traces equal lengh?

Best Regard