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Altera_Forum
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9 years ago

ALTLVDS_RX->LVDS serdes Link Training

Implementing Receiver interface. From transmitter we have 8 LVDS data channel and 1 LVDS sync channel. From sync channel we use to get training pattern which will be available in data channel for lin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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I assume it is merging the PLL for each altlvds_rx instance, so they are all driven by a single PLL and all aligned. (If they each required their own PLL, it would not fit.)

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Hello Rysc,

If i have three seperated ADC(LVDS output type) processed by FPGA, can i merge all of them into one altlvds_rx module?

Best Regards