ALTLVDS_RX->LVDS serdes Link Training

576 Mbps can be met by all speed grades. Look at the fHSDR spec, which is 875Mbps, 850 and 640 for the different speed grades. Note that the sampling window is 350ps for each one, which means the data only needs to be stable around the clock edge for 350ps. (Other reasons limit the Fmax, since 350ps is technically ~2.8G) Use the altlvds_rx IP with deserialization of 8 and you'll be fine. (There are board layout restrictions since this uses dedicated hardware, specifically a dedicated clock tree from the PLL to the IO to guarantee low skew and ODV). Your system may not even need word alignment(if the words are spread across each channel, so each cycle is a new word, then you're good.) There are a few other cases. But let's say each channel is bringing in its own 8 bit word, so when it's deserialized the output may not be word aligned. You will need to rx channel data align to slip it. (I've seen user's do this in logic too, but no need to)