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It rather depends on the transmitting device. Unfortunately the OP didn't tell us what device it is. I have closed 600 Mbps in Cyclone II, the source devices were TI octal ADCs using a home-made deserialiser. Here is an image of the board with 16 ADCs:
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Agreed. I assumed the OP was using a high-speed image sensor because he mentioned a sync channel. I've been working with high-speed image sensors for many years now and most of them come with shockingly incomplete data sheets. I designed one sensor interface without DPA but I didn't do it by closing timing. That would have been impossible due to lack of detailed enough timing specs in the sensor data sheet. Instead I designed a state machine that performed a bit timing calibration by cycling through all 8 phases of the sampling clock and observing the parallel data out of the ALTLVDS_RX blocks to determine the optimal clock phase for sampling the data. The timing would drift during operation and we would start getting errors, so ended up having to re-calibrate the interface every video frame during the dead time between frames.
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