Honored ContributorI am using an altlvds_rx mega-function with Arria V.
How does the reciever's output data is ordered with respect to the serial input data, MSB/LSB first? meaning, if i use a SERDES factor of 2, and the serial input data is '1' followed by '0', is the output "01" or "10"? Thanks. [/INDENT]
Honored ContributorNote that altlvds_rx with a deserialization of /2 will be built with generic logic, i.e. an altddr_input block to capture the data, and a PLL that drives a global clock tree. The timing is not very good with this layout(although I believe a large portion is due to overly-pessimistic timing models for skew analysis). If you go to a higher serialization rate, such as /4, the timing is excellent. I think you get a sampling window of 300ps, and this is because all the dedicated LVDS hardware is used(a very low skew, dedicated clock tree, a register that samples at the higher rate so there's no rise/fall variation). I've seen on more than one occasion where a user that really only needs /2 deserialization instead build an altlvds block with /4 deserialization.
As to your question, the data is serial, so just looking at it by itself you could never determine the order. I believe what you're asking is it's relation to the external clock. The MSB output is what is captured by the rising edge, so if you'r sending clock/data center-aligned, it's the one that lines up with the rising edge. If sending edge-aligned I believe it's the one coming after the rising edge, since the clock will be shifted 90 degrees in time. (If you're simulating, you'll know in a second, and even in hardware you'll probably be able to quickly determine if it's right or not, and its easy to switch.)Honored Contributori am actualy using /6 factor, i asked about /2 to simplify my question.
what i am asking is simple, if the serial data at the altlvds_rx is '0' followed by '1', what would the parallel altlvds_rx output be: "01" or "10"?Honored ContributorI believe the dedicated LVDS hardware just loads it serially into a FIFO(shift register) and you read it out in parallel, so the first one in is the MSB. In the /2 example, I was just pointing out that 01 and 10 are not the only two possibilities. Even if the first in correlates to the higher order bit, you could still have x0 come out first, then 1x, depending on the data relation to the clock.
Honored Contributoryou may simulate this IP, then you know it
