Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

ALTLVDS buffer implementation

I'm using an altlvds_rx receiver in Cyclone III with external PLL. For the buffer implementation I can choose between RAM, MUX and LE. Could there be a reason to make a choice other than resource usa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

--- Quote Start ---

Do you know if there's any detailed additional information on this topic?

--- Quote End ---

I fear, there isn't. I was surprized myself, when I was aware of the special properties of the odd factor LVDS receiver and looked inside the generated RTL. I decided, that it wasn't an appropriate solution for my problem. Generally, because Cyclone soft LVDS is based on double data rate (DDIO) registers, the fast clock can be aligned with the slow clock only for every second data word. So some kind of special processing is required.

Regards, Frank