ALTGX for A2GX always outputs K28.5- ?!

I have found a solution to my problem. On the contrary to what is told in the A2GX manual (Figure 4-3), tx_digitalreset must NOT be deasserted right after pll_locked goes to 1 but some delay must be added.

I delayed 16 clocks (@ 100 MHz) tx_digitalreset deassertion after pll_locked goes high. The ALTGX now quits outputting K.28.5- and K.28.6- and starts outputting the real data I am feeding to it.

Great that I found it, sad that, once again, I'm losing time fixing somebody else's bugs.