altera transceiver support burst mode?

Hi Rick,

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As far as I know, the FPGA is not good to work in burst mode (i mean it need long to lock. I tested the stragix ii gx transceivers, from poweron to plllock - 41.28us, from rx_analogrest to rx_pll 30us and to rx_lockfreq need another 419.59us: you know it's really terrible).

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Those parameters are of interest for the system design. But they are not the timing parameters you really care about for your original question (as I see it anyway).

What you want to know is; given that the CDR PLLs are locked to the PLLREF clock, how long does it take for the CDR PLL to determine that an incoming data pre-amble is sufficient for lock-to-data to occur? Once LTD has occurred, you can switch over to using the recovered clock, and the CDR can recover real data.

See if you can determine that timing parameter.

Cheers,

Dave