Forum Discussion
Altera_Forum
Honored Contributor
14 years ago --- Quote Start --- Hi Rick, Ok, so the lock-to-reference and lock-to-data modes would be needed. You can configure the Stratix IV GX transceivers as manual or automatic. The Stratix II GX might be different, I have not looked at their data sheets. Given that you control the preamble, it should be possible to make it work. Listen to the transceiver webinar on the Altera web site. I think its the 2.5hr one. It has a nice overview of all the transceiver features. Lets see if I can find it: This one is 0.5 hrs: http://www.altera.com/education/training/courses/osiigx1115 This one is 2.5 hrs: http://www.altera.com/education/training/courses/o40nm1110 I'm pretty sure these both had comments on LTD and LTR modes. Just skip the boring parts :) I will, thanks! Cheers, Dave --- Quote End --- Thanks Dave, I will check them out. As far as I know, the FPGA is not good to work in burst mode (i mean it need long to lock. I tested the stragix ii gx transceivers, from poweron to plllock - 41.28us, from rx_analogrest to rx_pll 30us and to rx_lockfreq need another 419.59us: you know it's really terrible). I have no idea how it has been improved in the stratix iv or higher. But it seems it performs pretty good in your case! Thanks. Rick