altera transceiver support burst mode?

Hi Rick,

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It's simply O/E or E/O conversion

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Ok, so the lock-to-reference and lock-to-data modes would be needed.

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It's pretty cool that you provide your design details. I really would like to look into the clocking methods you mentioned: lock-to-reference, or lock-to-data. Can the clock methods choose by configuration or external control?

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You can configure the Stratix IV GX transceivers as manual or automatic. The Stratix II GX might be different, I have not looked at their data sheets.

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The preamble could be programmed by myself. Still, I have no idea how long it needs to be the worse case lock-to-data. I will check it out soon with two dev boards with Altera Stratix II GX FPGA.

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Given that you control the preamble, it should be possible to make it work.

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Where can I get more information or datasheet of clocking methods?

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Listen to the transceiver webinar on the Altera web site. I think its the 2.5hr one. It has a nice overview of all the transceiver features.

Lets see if I can find it:

This one is 0.5 hrs:

http://www.altera.com/education/training/courses/osiigx1115

This one is 2.5 hrs:

http://www.altera.com/education/training/courses/o40nm1110

I'm pretty sure these both had comments on LTD and LTR modes. Just skip the boring parts :)

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If you have any questions on the high speed operation like 10GE, let me know.

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I will, thanks!

Cheers,

Dave