altera transceiver support burst mode?

--- Quote Start ---

Hi Rick,

I have heard of it, but have never looked at any of the details.

What you describe occurs on the fiber. What happens at the optical-to-electrical interface? Is it simply optical-to-electrical conversion of whatever is on the fiber, or is something smarter used?

--- Quote End ---

It's simply O/E or E/O conversion, without smarter used. Or, you have to get specified burst mode CDR chips for providing recovered clk and data. Actually, I don't want to do this since I need to redesign the board. That's why I ask for some details of FPGA and it's capability to support burst mode operation.

--- Quote Start ---

I use basic mode. There are two clocking methods that I need to investigate; lock-to-reference and lock-to-data. In lock-to-reference, the transceiver PLLs lock to an external reference clock and ignore the CDR recovered clock (if there is one), otherwise you can switch to a recovered clock (in lock-to-data mode). There are status bits in the transceiver block that indicate whether there is a CDR PLL lock. It sounds like you could use something similar; when there is no traffic, and the CDR PLLs lose lock-to-data, switch them back to lock-to-reference, then when data comes, they can go back to lock-to-data.

What you would need to investigate is how fast this can happen, and whether or not it will be sufficient to capture traffic. Given that the packet contains preambles, I suspect they are there for lock-to-data to occur. If you know the preamble length, and the worst-case lock-to-data time, you will be able to determine if it can work.

Cheers,

Dave

--- Quote End ---

It's pretty cool that you provide your design details. I really would like to look into the clocking methods you mentioned: lock-to-reference, or lock-to-data. Can the clock methods choose by configuration or external control? The preamble could be programmed by myself. Still, I have no idea how long it needs to be the worse case lock-to-data. I will check it out soon with two dev boards with Altera Stratix II GX FPGA.

Where can I get more information or datasheet of clocking methods ? Thank you. If you have any questions on the high speed operation like 10GE, let me know.

Rick