Altera Soft LVDS IP core (output not consistent with the input)

@IDeyn @RSree Thanks for the replies.

@IDeyn

1. Yes I have tried bit slip mode. But the issue is that bitslip is not constant neither the frequency of change in bitslip. So have not been able to figure out how to do link training using the bit slip mode in this case.
2. The input clock (rx_inclock) I have chosen in IP core configuration is 200 MHz. The internal PLL generates the rx_outclock of 25 MHz.
3. I have tried two different data rates 200 Mbps and 16 Mbps at multiple input clock rates.

Further, during simulation, I am transmitting the serial bit stream from a testbench using a 200 MHz clock. And the same clock is being fed to the LVDS IP core, so I don't see any phase error being induced in this case. So cause of bitslip seems to be somewhere else.

@Rsree Yes I am simulating the stand alone LVDS IP core.