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SMS's avatar
SMS
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7 years ago

Altera Soft LVDS IP core (output not consistent with the input)

I am simulating the Soft LVDS IP core as receiver by passing a bit stream with IP core parameters configured as follows: Power Supply Mode: Dual (for 10M50DAF484C7G) Functional mode: RX Number of ...
IDeyn's avatar
IDeyn
Icon for Contributor rankContributor
7 years ago

Hi SMS.

First of all, I would recommend to look at that video - https://www.youtube.com/watch?v=02lgfcxSjQA&t=45s

It's somewhat not exactly what you are doing (14-bit shown here is more complicated), but it contents also example design which you can examine with Signal Tap and ISSP for quick iterative testing.

  1. Had you tried bit slip mode?
  2. Which clocks your internal pll generates?
  3. Which output data rate did you choose?

The inclock frequency depends on the output data rate (input data rate & deserialization factor).

You can check in similar IP core datasheet here - https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altlvds.pdf

Best regards,

Ivan