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Altera_Forum's avatar
Altera_Forum
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10 years ago

Altera SGDMA & TSE

Hi all, I am working on TSE and is using sgdma for avalon_stream_to_mem descriptor, now in my code I have four descriptors,I am receiving network packets in my local buffer from sgdma in every sgd...
Msg06484's avatar
Msg06484
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2 years ago

Hi,

I hope it is ok to append to this chat, I am new to this forum. My question is similar but more basic so I thought this might be the place to ask.

I have the lwip core. I have the sample design for the Cyclone IV E, found at https://github.com/adwinying/lwIP-NIOSII/tree/master/FPGA/software/lwIP_NIOS_II_Example

I am tying to develop this for the Arria10 in Quartus 18.1

I first instantiated the sgdma and found that the lwip does not like that...

I then found that it does like msgdma so I instantiated that, but still there are errors. Things like - ALTERA_TSE_SGDMA_INTR_MASK and ALTERA_TSE_FIRST_RX_MSGDMA_DESC_OFST

If I am telling the truth I also instantiated on chip memory (RAM) for the dma, and a descriptor_memory ROM.

I am the only person in the company on this project right now. I have access to a corporate tech support at Intel, but we are stuggling.

Does anyone know of a sample design that would be more fitting for lwip on Quartus 18 (possibly with arria10)?

Thanks in advance.