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Altera_Forum
Honored Contributor
Honored Contributoraltera_pll + altlvds_rx = problems with fitting
Hello forum, i wanna create a lvds reciever with deserializer logic, iam using Cyclone 5 E (5cefa7f31i7n). I try to create 1 pll in 5B bank (lvds mode with 8 clkouts), and 4 altlvds_rx, in between...
Altera_ForumHonored Contributor
Honored ContributorRemove all the pin assignments and let it autofit.
If it can fit, see if it is as supernode mentioned OR if you are following the placement rule as certain PLL only supports one edge but not across edge. Example: Right corner PLL support LVDS on Right edge. If it still cannot fit, i think most probably it is due to the PLL cannot support as many channels on that particular edge.
