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Altera_Forum
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11 years ago

altera_pll + altlvds_rx = problems with fitting

Hello forum, i wanna create a lvds reciever with deserializer logic, iam using Cyclone 5 E (5cefa7f31i7n). I try to create 1 pll in 5B bank (lvds mode with 8 clkouts), and 4 altlvds_rx, in between...
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Altera_Forum
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11 years ago

I am not that familiar with the CV devices, but ArriaV uses dedicated clock structures for LVDS RX clocking. There are some restrictions that say that multiple clocks cannot be interleaved on a single bank. Check you device datasheet for details.