altera modelsim timing simulation error

hi guys.

i got an error after running the timing simulation for my module, as shown below:

# vlog -vlog01compat -work work +incdir+. {MATRIXVECTORMULT_1ROW_fast.vo}# Model Technology ModelSim ALTERA vlog 10.0c Compiler 2011.09 Sep 21 2011# -- Compiling module MATRIXVECTORMULT_1ROW_RAM# ** Error: MATRIXVECTORMULT_1ROW_fast.vo(11923): Bit-select into 'y' is out of bounds.# ** Error: MATRIXVECTORMULT_1ROW_fast.vo(11959): Bit-select into 'y' is out of bounds.# ** Error: MATRIXVECTORMULT_1ROW_fast.vo(11995): Bit-select into 'y' is out of bounds.# ** Error: MATRIXVECTORMULT_1ROW_fast.vo(12031): Bit-select into 'y' is out of bounds.# ** Error: MATRIXVECTORMULT_1ROW_fast.vo(12067): Bit-select into 'y' is out of bounds.# ** Error: MATRIXVECTORMULT_1ROW_fast.vo(12103): Bit-select into 'y' is out of bounds.# ** Error: MATRIXVECTORMULT_1ROW_fast.vo(12139): Bit-select into 'y' is out of bounds.# ** Error: MATRIXVECTORMULT_1ROW_fast.vo(12175): Bit-select into 'y' is out of bounds.# ** Error: MATRIXVECTORMULT_1ROW_fast.vo(12211): Bit-select into 'y' is out of bounds.# ** Error: MATRIXVECTORMULT_1ROW_fast.vo(12247): Bit-select into 'y' is out of bounds.# ** Error: MATRIXVECTORMULT_1ROW_fast.vo(12283): Bit-select into 'y' is out of bounds.# ** Error: MATRIXVECTORMULT_1ROW_fast.vo(12319): Bit-select into 'y' is out of bounds.# ** Error: C:/altera/11.1/modelsim_ase/win32aloem/vlog failed.# Error in macro ./MATRIXVECTORMULT_1ROW_run_msim_gate_verilog.do line 8# C:/altera/11.1/modelsim_ase/win32aloem/vlog failed.# while executing# "vlog -vlog01compat -work work +incdir+. {MATRIXVECTORMULT_1ROW_fast.vo}"

here is the verilog code for my module:

module MATRIXVECTORMULT_1ROW_RAM (clk, reset, start, dataina, datainb, done, y, iCV, addressa, addressb, MULT_OUT, R1, Y);

input clk, reset, start;

input [7:0] dataina, datainb;

output done;

output [3:0] y, addressa, addressb;

output [8:0] iCV;

output [15:0] MULT_OUT, R1, Y;

DU_1ROW_RAM datapath (clk, reset, iCV[8], iCV[7], iCV[6], iCV[5], iCV[4], iCV[3], iCV[2], iCV[1], iCV[0], dataina,

datainb, addressa, addressb, MULT_OUT, R1, Y);

CU_1ROW_RAM controller (clk, reset, start, done, y, iCV);

endmodule

and my testbench code:

`timescale 1ns/1ns

module testbench_matrixvectormult_1row_ram();

reg clk, reset, start;

reg [7:0] dataina, datainb;

wire done;

wire [3:0] y, addressa, addressb;

wire [8:0] iCV;

wire [15:0] MULT_OUT, R1, Y;

MATRIXVECTORMULT_1ROW_RAM matrixvectormult_1row_ram (.clk(clk), .reset(reset), .start(start), .dataina(dataina), .datainb(datainb), .done(done), .y(y), .iCV(iCV), .addressa(addressa), .addressb(addressb), .MULT_OUT(MULT_OUT), .R1(R1), .Y(Y));

initial

begin

clk = 1; reset = 1; start = 0;

$monitor ($time, "clk%b, reset%b, start%b, dataina%b, datainb%b, done%b, y%b, iCV%b, addressa%b, addressb%b, MULT_OUT%b, R1%b, Y%b",

clk, reset, start, dataina, datainb, done, y, iCV, addressa, addressb, MULT_OUT, R1, Y);

end

always# 20 clk = !clk;

initial

begin

# 20 reset = 0; start = 1; dataina = 8'h01; datainb = 8'h01; //20ns

# 40 start = 0; //60ns

# 80 dataina = 8'h02; datainb = 8'h02; //140ns

# 120 dataina = 8'h03; datainb = 8'h03; //260ns

# 120 dataina = 8'h04; datainb = 8'h04; //380ns

# 240 reset = 1; //620ns

end

endmodule

the functional simulation run just fine. can anybody help?