Altera MAX 3064 CPLD weird problem

If your timing analysis is successful then the main culprit is that your asynch signals have glitches from outside.

You can apply a patch: design a basic test to ignore these glitches for example register the asynch signal or decide the edge only if it is more than one clk period or so.

-- this code tests asynch signal being high at two successive clock edges

-- Combinatorial logic for positive edge_to_pulse
PROCESS (irq_src_reg_q2,irq_src_reg_q3, irq_src_reg_q4) IS
BEGIN
FOR i IN 0 TO 6 LOOP
     irq_src_reg_posedge(i) <= irq_src_reg_q2(i) and irq_src_reg_q3(i) and not irq_src_reg_q4(i);
END LOOP;
END PROCESS;