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Altera_Forum
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17 years ago

Altera MAX 3064 CPLD weird problem

Hi, I'm using Altera MAX3000 series (EPM3064-10 to be exact) with CPLD_CLK = 77.5Mhz, and I have a very weird problem... pseudocode is below: signal_abc = asynchronous from external c...
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Altera_Forum
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17 years ago

btw, I only noticed these glitches when we changed our system clock to 77.5Mhz. when previously running at 51Mhz, I never encountered this issue...

the loop there is to repeat the entire flops for the whole 7-bit arrays (including the clear register)...

hmm... I can try to re-flop the posedge register...