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Altera_Forum
Honored Contributor
17 years agoAltera MAX 3064 CPLD weird problem
Hi, I'm using Altera MAX3000 series (EPM3064-10 to be exact) with CPLD_CLK = 77.5Mhz, and I have a very weird problem... pseudocode is below: signal_abc = asynchronous from external c...
Altera_Forum
Honored Contributor
17 years agoWith regard to for loop in:
interrupt_trigger: PROCESS (rst_n, clk, irq_clr_reg) IS
BEGIN
FOR i IN 0 to 6 LOOP
IF (rst_n = '0' OR irq_clr_reg(i) = '1') THEN
irq_trig_reg(i) <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (irq_src_reg_posedge(i) = '1') THEN
irq_trig_reg(i) <= '1';
END IF;
END IF;
END LOOP;
END PROCESS interrupt_trigger
Ia it possible that this may go wrong: why not put the loop start after clk edge, just a thought