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Altera_Forum
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16 years ago

Altera MAX 3064 CPLD weird problem

Hi, I'm using Altera MAX3000 series (EPM3064-10 to be exact) with CPLD_CLK = 77.5Mhz, and I have a very weird problem... pseudocode is below: signal_abc = asynchronous from external c...
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Altera_Forum
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16 years ago

Hi,

Sorry you are right you have indeed double registers(q2/q3). So I withdraw my first feel.

Your code looks sound to me so far. The fact that the error is related to succession of asynch signal points to a possible glitch of irq_src_reg_posedge

which is then registered as irq_trig_reg. It is now matter of speculations. But I will register the edge detection itself just in case.