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Altera_Forum
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17 years ago

Altera MAX 3064 CPLD weird problem

Hi, I'm using Altera MAX3000 series (EPM3064-10 to be exact) with CPLD_CLK = 77.5Mhz, and I have a very weird problem... pseudocode is below: signal_abc = asynchronous from external c...
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Altera_Forum
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17 years ago

but this is to generate 1-clock-cycle wide of pulse when there's a rising-edge.

I already made sure each bit went through double-flops before being used...