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Altera_Forum
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16 years ago

Altera MAX 3064 CPLD weird problem

Hi, I'm using Altera MAX3000 series (EPM3064-10 to be exact) with CPLD_CLK = 77.5Mhz, and I have a very weird problem... pseudocode is below: signal_abc = asynchronous from external c...
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Altera_Forum
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16 years ago

Hi,

For now I feel there is a problem here, this is combinatorial(unlike pseudocode) 


-- Combinatorial logic for positive edge_to_pulse
PROCESS (irq_src_reg_q2, irq_src_reg_q3) IS
BEGIN
FOR i IN 0 TO 6 LOOP
irq_src_reg_posedge(i) <= irq_src_reg_q2(i) and not irq_src_reg_q3(i);
END LOOP;
END PROCESS;

it will get you in trouble if there is any glitch