Altera MAX 3064 CPLD weird problem

sure, in the entity:

irq_src_reg <= wlan_irq & NOT sdio_irq_n & NOT fb_n & sw_irq & NOT overcurr_n & headlift & NOT pb_n; -- these are external signals

PROCESS (rst_n, clk) IS

BEGIN

IF (rst_n = '0') THEN

irq_src_reg_q (6 downto 0) <= (OTHERS => '0');

irq_src_reg_q2 (6 downto 0) <= (OTHERS => '0');

irq_src_reg_q3 (6 downto 0) <= (OTHERS => '0');

irq_n <= '1';

ELSIF (clk'event and clk = '1') THEN

irq_src_reg_q (6 downto 0) <= irq_src_reg (6 downto 0);

irq_src_reg_q2 (6 downto 0) <= irq_src_reg_q (6 downto 0);

irq_src_reg_q3 (6 downto 0) <= irq_src_reg_q2(6 downto 0);

irq_n <= NOT (irq_trig_reg(6) OR irq_trig_reg(5) OR irq_trig_reg(4) OR irq_trig_reg(3) OR irq_trig_reg(2) OR irq_trig_reg(1) OR irq_trig_reg(0));

END IF;

END PROCESS;

-- Combinatorial logic for positive edge_to_pulse

PROCESS (irq_src_reg_q2, irq_src_reg_q3) IS

BEGIN

FOR i IN 0 TO 6 LOOP

irq_src_reg_posedge(i) <= irq_src_reg_q2(i) and not irq_src_reg_q3(i);

END LOOP;

END PROCESS;

irq_clr_reg <= data(6 DOWNTO 0)

WHEN (cs_n = '0' AND we_n = '0' AND addr = irq_clr_reg_addr)

ELSE (OTHERS => '0')

-- data is inout(7 downto 0) at top-level

data <= 'Z' & irq_trig_reg

WHEN ((cs_n = '0') AND (oe_n = '0') AND (addr = irq_trig_reg_addr))

ELSE (OTHERS => 'Z')

interrupt_trigger: PROCESS (rst_n, clk, irq_clr_reg) IS

BEGIN

FOR i IN 0 to 6 LOOP

IF (rst_n = '0' OR irq_clr_reg(i) = '1') THEN

irq_trig_reg(i) <= '0';

ELSIF (clk'EVENT AND clk = '1') THEN

IF (irq_src_reg_posedge(i) = '1') THEN

irq_trig_reg(i) <= '1';

END IF;

END IF;

END LOOP;

END PROCESS interrupt_trigger